Register Descriptions; Frequency Control Register (Frqcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.4

Register Descriptions

Table 6.6 shows the register configuration of the clock pulse generator.
Table 6.6 Register Configuration
Register Name Abbreviation
Frequency control FRQCR
register
6.4.1

Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin during normal
operation mode, change of gain of crystal oscillator for the XTAL pin, software standby mode, deep standby mode, and
standby mode cancellation. The register specifies the frequency division ratio for the CPU clock (Iφ). FRQCR can be
accessed in 16-bit units.
Bit: 15
-
0
Initial value:
R/W:
R
Bit Bit Name
15 ―
14 CKOEN2
13, 12 CKOEN[1:0]
11, 10 ―
9, 8 IFC[1:0]
7, 6 ―
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
R/W Initial Value
R/W H'0335
14 13 12 11 10
CKO
CKOEN[1:0] - -
EN2
0 0 0 0 0
R/W R/W R/W R R
Initial
Value R/W
0 R
0 R/W
00 R/W
00 R
11 R/W
00 R
9 8 7 6 5
IFC[1:0] - - -
1 1 0 0 1
R/W R/W R R R
Description
Reserved
This bit is always read as 0. The write value should always be 0.
Clock Output Enable 2
Specifies whether the CKIO pin outputs clock signals or is fixed to the low
level when the gain of the crystal oscillator for the XTAL pin is changed.
If this bit is set to 1, the CKIO pin is fixed to the low level when the gain of
the crystal oscillator for the XTAL pin is changed. Therefore, the
malfunction of an external circuit caused by an unstable CKIO clock while
changing the gain of the crystal oscillator for the XTAL pin can be
prevented.
0: Unstable clock output
1: Low-level output
Clock Output Enable
These bits specify whether the CKIO pin outputs clock signals, or is set to
a fixed level or high impedance (Hi-Z) during normal operation mode,
deep standby mode, software standby mode, or cancellation of standby
mode.
If these bits are set to 01, the CKIO pin is fixed at low during deep
standby mode, software standby mode, or cancellation of software
standby mode. Therefore, the malfunction of an external circuit caused by
an unstable CKIO clock during cancellation of software standby mode
can be prevented.
Table 6.7 lists CKOEN[1:0] settings.
Reserved
These bits are always read as 0. The write value should always be 0.
CPU Clock Frequency Division Ratio
These bits specify the frequency division ratio of the CPU clock with
respect to the output frequency of PLL circuit. Note: See section 6.5.1.
00: 1/1 time
01: 2/3 time
10: Reserved (setting prohibited)
11: 1/3 time
Reserved
These bits are always read as 0. The write value should always be 0.
6. Clock Pulse Generator
Address Access Size
H'FCFE0010 16
4 3 2 1 0
- - - - -
1 0 1 0 1
R R R R R
6-7