Interrupt Control Register 1 (Icr1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.3.2

Interrupt Control Register 1 (ICR1)

ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually:
low level, falling edge, rising edge, or both edges.
Bit: 15
IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
R/W:
R/W
Bit Bit Name
15 IRQ71S
14 IRQ70S
13 IRQ61S
12 IRQ60S
11 IRQ51S
10 IRQ50S
9 IRQ41S
8 IRQ40S
7 IRQ31S
6 IRQ30S
5 IRQ21S
4 IRQ20S
3 IRQ11S
2 IRQ10S
1 IRQ01S
0 IRQ00S
[Legend]
n = 7 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
9 8 7 6
0 0 0 0
R/W R/W R/W R/W R/W
Description
IRQ Sense Select
These bits select whether interrupt signals corresponding to pins IRQ7 to
IRQ0 are detected by a low level, falling edge, rising edge, or both edges.
00: Interrupt request is detected on low level of IRQn input
01: Interrupt request is detected on falling edge of IRQn input
10: Interrupt request is detected on rising edge of IRQn input
11: Interrupt request is detected on both edges of IRQn input
7. Interrupt Controller
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W
0
0
R/W
7-14