Digital Noise-Filter Circuits - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.8

Digital Noise-Filter Circuits

Figure 18.23 is a block diagram of the digital noise-filter circuit. When the NFE bit in the RIICnFER
register is set to 1, input to the RIICnSCL and RIICnSDA pins are conveyed to the internal circuitry
through digital noise-filter circuits.
The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in
series and a match-detection circuit.
The number of effective stages in the digital noise filter is selected by the RIICnMR3.NF[1:0] bits. The
selected number of effective stages determines the noise-filtering capability as a period from one to
four IICφ cycles.
The input signal to the RIICnSCL pin (or RIICnSDA pin) is sampled on falling edges of the IICφ
signal. When the input signal level matches the output level of the number of effective flip-flop circuit
stages as selected by the RIICnMR3.NF[1:0] bits, the signal level is conveyed to the subsequent stage.
If the signal levels do not match, the previous value is retained.
Note that if the ratio of the frequencies for P0φ and IICφ is small (when the RIICnMR1.CKS[2:0] bits
are set to "000
noise filter.
RIICnSCL/
RIICnSDA
input signal
NFE: Digital noise filter circuit enable bit
NF[1:0]: Digital noise filter stage selection bits
Figure 18.23
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
"), even necessary signals might be eliminated due to the characteristics of the digital
B
Four-stage digital noise filter
D Q D Q D Q
CLK CLK CLK
IICφ
Block Diagram of Digital Noise Filter Circuit
Mismatch
D Q D Q
CLK CLK
NF[1:0]
18. I²C Bus Interface
RIICnSCL/
RIICnSDA
Match D Q
internal signal
CLK
P0φ
NFE
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