Input/Output Pins - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.2

Input/Output Pins

Table 19.1 shows the pin assignments relating to this module.
Table 19.1 Pin Assignments
Channel Pin Name
0, 1, 3 SSISCK0*
SSISCK3*
1
SSIWS0*
1
SSIWS3*
SSITxD0, SSITxD1,
SSITxD3
SSIRxD0*
SSIRxD3*
2 SSISCK2*
1
SSIWS2*
SSIDATA2*
Common AUDIO_CLK*
AUDIO_X1
AUDIO_X2
Note 1. In slave mode, whether or not to use the noise canceler in the input route can be selected. For details, refer to section 41.3.15,
Serial Sound Interface Noise Canceler Control Register (SNCR), under section 41, Ports.
Note 2. When the SSInCKS bit (n = 0 to 3) is set to 1, the MLB_CLK pin is used as the AUDIO_CLK pin. For details, refer to section
37.3.70, SSI Pin Mode Register (SSIPMD_CIM) and section 37.4.4, Pin Connection Specifications of SSIF.
Note 3. Each of SSIF1 to SSIF3 can use SSISCK0 and SSIWS0 of SSIF0 as its own SSISCK and SSIWS. For details, refer to section
37.3.70, SSI Pin Mode Register (SSIPMD_CIM) and section 37.4.4, Pin Connection Specifications of SSIF. When SSIF1 to
SSIF3 uses SSIF0 as the master, the noise canceler function cannot be used.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
1 3 1 3
* , SSISCK1* * ,
1 3
*
3 1 3
* , SSIWS1* * ,
3
*
1 1
, SSIRxD1* ,
1
1 3
*
3
*
1
2
I/O Description
I/O Serial bit clock
I/O Word selection
Output Serial data output
Input Serial data input
I/O Serial bit clock
I/O Word selection
I/O Serial data input/output
Input External clock for audio (input oversampling clock)
Input Crystal resonator/external clock for audio (input oversampling
clock)
Output
19. Serial Sound Interface
19-3