Input/Output Pins; Register Description - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
20.2

Input/Output Pins

Table 20.1 shows the pin configuration.
Table 20.1 Pin Configuration
Pin Name
MLB_CLK
MLB_SIG
MLB_DAT
20.3

Register Description

Table 20.2 shows the register configuration.
For details on the registers, contact Renesas Electronics Corporation's sales office.
Table 20.2 Register Configuration
Register Name
Configuration Device control configuration register
control register
System status configuration register
System data configuration register
System mask configuration register
Version control configuration register
Synchronous base address configuration
register
Asynchronous base address configuration
register
Control base address configuration register
Isochronous base address configuration
register
Channel interrupt configuration register
2
Channel m* Channel m entry configuration register
configuration
Channel m status configuration register
register
Channel m current buffer configuration
register
Channel m next buffer configuration register
Local channel m buffer configuration register
Note 1. Contact Renesas Electronics Corporation's sales office.
Note 2. Each channel of the media local bus is identified by "m" (m = 0 to 30).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
I/O Description
I MediaLB clock input
I/O MediaLB signal information I/O
I/O MediaLB data I/O
Abbreviation R/W
DCCR
SSCR
SDCR
SMCR
VCCR
SBCR
ABCR
CBCR
IBCR
CICR
CECRm
CSCRm
CCBCRm
CNBCRm
LCBCRm
Initial
Value Address
*1 *1
H'E8034000
*1 *1
H'E8034004
*1 *1
H'E8034008
*1 *1
H'E803400C
*1 *1
H'E803401C
*1 *1
H'E8034020
*1 *1
H'E8034024
*1 *1
H'E8034028
*1 *1
H'E803402C
*1 *1
H'E8034030
*1 *1
H'E8034040 + m x 10
*1 *1
H'E8034044 + m x 10
*1 *1
H'E8034048 + m x 10
*1 *1
H'E803404C + m x 10
*1 *1
H'E8034280 + m x 4
20. Media Local Bus
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
20-2