Internal Clock Signals (1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.10.5

Internal Clock Signals (1)

CPU clock
(Iφ max. 400.00 MHz)
Internal bus clock
(Bφ max. 133.33 MHz)
Peripheral clock 1
(P1φ max. 66.67 MHz)
Figure 6.9 Distribution of Internal Clock Signals (1)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
CPU
Module standby signals
Secondary cache
SPI multi I/O bus controller
Ethernet controller
EthernetAVB (RZ/A1LU only)
Media local bus (RZ/A1L only)
Video display controller 5
JPEG codec unit (RZ/A1LU only)
Capture engine unit
Internal buses (north main bus, AXI64IC2 bus,
AHB32IC3 bus, peripheral bus 6, south main bus,
AXI128IC2 bus, AXI128IC3 bus)
Interrupt controller
Direct memory access controller
Large-capacity on-chip RAM
Module standby signals
Debugger interface (CoreSight)
USB 2.0 host/function interface, 2 channels
A/D converter
CD-ROM decoder (RZ/A1L only)
SD host interface
MMC host interface
Serial sound interface, 4 channels
SCUX
Renesas serial peripheral interface, 3 channels
Renesas SPDIF
Media local bus (RZ/A1L only)
Video display controller 5
JPEG codec unit (RZ/A1LU only)
Internal buses (peripheral buses 3, 4, 5, and 7)
General input/output port
Bus state controller
6. Clock Pulse Generator
6-18