Address Map - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.4

Address Map

Table 5.5 shows the address map of this LSI.
Table 5.5 Address Map
Address
0xFFFF_0000 to
0xFFFF_FFFF
0xFD00_0000 to
0xFFFE_FFFF
0xFCFF_0000 to
0xFCFF_FFFF
0xFCFE_0000 to
0xFCFE_FFFF
0xFC08_0000 to
0xFCFD_FFFF
0xFC00_0000 to
0xFC07_FFFF
0xF000_2000 to
0xFBFF_FFFF
0xF000_0000 to
0xF000_1FFF
0xE823_0000 to
0xEFFF_FFFF
0xE820_0000 to
0xE822_FFFF
0xE805_0000 to
0xE81F_FFFF
0xE803_0000 to
0xE804_FFFF
0xE802_0000 to
0xE802_FFFF
0xE800_0000 to
0xE801_FFFF
0xE000_0000 to
0xE7FF_FFFF
0x6030_0000 to
0xDFFF_FFFF
0x6020_0000 to
0x602F_FFFF
0x6018_0000 to
0x601F_FFFF
0x6010_0000 to
0x6017_FFFF
0x6008_0000 to
0x600F_FFFF
0x6002_0000 to
0x6007_FFFF
0x6000_0000 to
0x6001_FFFF
0x5C00_0000 to
0x5FFF_FFFF
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Area
I/O area
Reserved area
I/O area
I/O area
Reserved area
I/O area
Reserved area
Cortex-A9 private area
Reserved area
I/O area
Reserved area
I/O area
Reserved area
I/O area
Reserved area
Reserved area
On-chip large-capacity RAM page 4
mirror area (1 Mbyte) (RZ/A1L and RZ/A1LU only)
On-chip large-capacity RAM page 3
mirror area (512 Kbytes)
On-chip large-capacity RAM page 2
mirror area (512 Kbytes)
On-chip large-capacity RAM page 1
mirror area (512 Kbytes)
On-chip large-capacity RAM page 0
(including on-chip data retention RAM) mirror area
(512 Kbytes)
Reserved area
Slave Area Viewed Slave Area Viewed
from North Main Bus from South Main Bus
Masters Masters
*1
ROM in SLV4 —
—
1
SLV0 *
*1
SLV1
—
*2, *4
SLV6
—
—
—
*1, *3
SLV4
—
*1
SLV2
—
*1
SLV3 —
—
—
SLV7 SLV7
SLV6
SLV8 SLV5
SLV4
SLV3
SLV2
— —
5. LSI Internal Bus
5-7