Rscan0Gtstctr - Global Test Control Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.62 RSCAN0GTSTCTR — Global Test Control Register
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 046C
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.81
Bit Position
31 to 1
0
ICBCTME Bit
When this bit is set to 1, a communication test is enabled between the channels for which the
CmICBCE bit (m = 0 or 1) in the RSCAN0GTSTCFG register has been set to 1. Modify the
ICBCTME bit only in global test mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RSCAN0GTSTCTR register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
ICBCTME Communication Test between Channels Enable
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — —
0 0 0 0
R R R R
0: Communication test between channels disabled
1: Communication test between channels enabled
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— — — —
0 0 0 0
R R R R
17 16
— —
0 0
R R
1 0
ICBCTM
—
E
0 0
R R/W
21-112