Control Register 1 (Rcr1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
13.3.16

Control Register 1 (RCR1)

RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag.
The CF flag remains undefined until the divider circuit is reset (the RESET and ADJ bits in RCR2 are set to 1). When
using the CF flag, make sure to reset the divider circuit beforehand.
The AF flag remains undefined until the value is set to an alarm register and a counter. When using the AF flag, make
sure to set the alarm register and counter beforehand.
Bit Bit Name
7 CF
—
6, 5
4 CIE
3 AIE
—
2, 1
0 AF
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
BIt: 7 6
CF -
Initial value: 0
Undefined
R/W: R/W R
Initial
Value R/W Description
Undefined R/W Carry Flag
Status flag that indicates that a carry has occurred. CF is set to 1 when a second
counter carry is generated or a 64-Hz counter carry is generated while reading
the 64-Hz counter A value read from the count register at this time cannot be
guaranteed; another read is required.
0: No carry of second counter or no carry of 64-Hz counter while reading 64-Hz
counter
[Clearing condition]
When 0 is written to CF
1: Carry of second counter or carry of 64-Hz counter while reading 64-Hz
counter
[Setting condition]
When a second counter carry is generated or a 64-Hz counter carry is
generated while reading the 64-Hz counter, or 1 is written to CF
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit enables an interrupt.
0: A carry interrupt is not generated when the CF flag is set to 1
1: A carry interrupt is generated when the CF flag is set to 1
0 R/W Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit enables an interrupt.
0: An alarm interrupt is not generated when the AF flag is set to 1
1: An alarm interrupt is generated when the AF flag is set to 1
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
Undefined R/W Alarm Flag
The AF flag is set when the alarm time, which is set by the alarm registers
(RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR whose
ENB bit is set to 1), and counters match.
0: Alarm registers and counters not match
[Clearing condition]
When 0 is written to AF
1: Alarm registers and counters match*
[Setting condition]
When alarm registers (only the registers with ENB bit set to 1) and counters
match
Note: * Writing 1 holds previous value.
5 4 3 2 1
- CIE AIE - -
0 0 0 0 0
Undefined
R R/W R/W R R
13. Realtime Clock
0
AF
R/W
13-12