Address Remapping; Overview; Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.5

Address Remapping

5.5.1

Overview

Execution in Cortex-A9 jumps to an exception vector placed in addresses 0x0000_0000 to 0x0000_001C when an
exception such as a reset or an interrupt occurs. The interrupt response time depends on the time to access the memory
connected to this area, and when low-speed memory is connected, the overhead is large. To avoid this, the exception
vectors can be remapped to the on-chip high-speed RAM by using the MMU or vector base address register, or the
address remapping function can be used to allocate the addresses where the exception vectors are placed to the on-chip
high-speed RAM.
Figure 5.4 show the address maps before and after address remapping.
0x43FF_FFFF
0x4000_0000
0x202F_FFFF
0x2000_0000
0x07FF_FFFF
0x0400_0000
0x03FF_FFFF
0x0000_0000
Note 1. The address range from 0x2020_0000 to 0x202F_FFFF (page 4) is reserved in the RZ/A1LC.
Note 2. The address range from 0x0020_0000 to 0x002F_FFFF (page 4) is reserved in the RZ/A1LC.
Figure 5.4 Address Remapping
5.5.2

Operation

Addresses are remapped by setting the AXI128 bit in the remap register to 0. After address remapping, pages 0 to 4
(pages 0 to 3 in the RZ/A1LC) of the on-chip large-capacity RAM are allocated to addresses 0x0000_0000 to
0x009F_FFFF. Note that the address range from 0x0030_0000 to 0x009F_FFFF (0x0020_0000 to 0x009F_FFFF in the
RZ/A1LC) is reserved. Do not access this area. To access the CS0 space after address remapping, use the mirror area for
the CS0 space.
During address remapping, access to addresses 0x0000_0000 to 0x009F_FFFF is prohibited. Accordingly, to modify the
remap register, use the following steps.
(1) Stop the bus masters except for Cortex-A9,
or make settings so that addresses 0x0000_0000 to 0x009F_FFFF are never accessed.
(2) Execute a program outside addresses 0x0000_0000 to 0x009F_FFFF.
(3) After modifying the value of the remap register, execute a dummy read of the remap register.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
CS0 space
(64 Mbytes)
mirror
.
.
.
On-chip large-capacity Address
RAM
remapping
pages 0 to 4 (3 Mbytes)
.
.
.
CS1 space
(64 Mbytes)
CS0 space
(64 Mbytes)
0x43FF_FFFF
CS0 space
(64 Mbytes)
mirror
0x4000_0000
.
.
.
0x202F_FFFF
On-chip large-capacity
RAM
pages 0 to 4 (3 Mbytes)
0x2000_0000
.
.
.
0x07FF_FFFF
CS1 space
(64 Mbytes)
0x0400_0000
0x03FF_FFFF CS0 space
(54 Mbytes)
0x00A0_0000
0x009F_FFFF Reserved area
0x002F_FFFF
On-chip large-capacity
RAM
pages 0 to 4 (3 Mbytes)
0x0000_0000
5. LSI Internal Bus
* 1
* 2
5-10