Next Link Address Register N (Nxla_N); Current Link Address Register N (Crla_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.12

Next Link Address Register n (NXLA_n)

This is a 32-bit register that sets the link address of DMA channel n (n = 0 to 15).
For information about the link mode, see section 9.6.3, Link Mode.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
0
Initial value:
R/W: R/W
Bit Initial
Bit Name Value
31 to 0 NXLA All 0
9.4.13

Current Link Address Register n (CRLA_n)

This is a 32-bit register that indicates the link address of DMA channel n (n = 0 to 15).
For information about the link mode, see section 9.6.3, Link Mode.
Bit: 31
Initial value: 0
R/W: R
Bit: 15
0
Initial value:
R/W:
R
Bit Initial
Bit Name Value
31 to 0 CRLA All 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
R/W Description
R/W Sets a link address. The low-order 2 bits are masked with 0s. Only an address aligned with a
4-byte boundary can be set.
30 29 28 27 26
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R R R R R
R/W Description
R Indicates the address of the currently executed descriptor.
25 24 23 22 21
NXLA
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
NXLA
0 0 0 0 0
R/W R/W R/W R/W R/W
25 24 23 22 21
CRLA
0 0 0 0 0
R R R R R
9 8 7 6 5
CRLA
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R R R R R
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