Scl Synchronization Circuit - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.6

SCL Synchronization Circuit

In generation of the SCL (clock) signal, the RIIC starts counting out the value for width at high level
specified in RIICnBRH when it detects a rising edge on the SCL line and drives the SCL line low once
counting of the width at high level is complete. When the RIIC detects the falling edge of the SCL line,
it starts counting out the width at low level period specified in RIICnBRL, and then stops driving the
SCL line (releases the line) once counting of the width at low level is complete. The SCL (clock) signal
is thus generated.
If multiple master devices are connected to the I
contention with another master device. In such cases, the master devices have to synchronize their SCL
signals. Since this synchronization of SCL signals must be bit by bit, the RIIC is equipped with a
facility (the SCL synchronization circuit) to obtain bit-by-bit synchronization of the SCL clock signals
by monitoring the SCL line during communication.
When the RIIC has detected a rising edge on the SCL line and thus started counting out the width at
high level specified in RIICnBRH, and the level on the SCL line falls because an SCL signal is being
generated by another master device, the RIIC stops counting when it detects the falling edge, drives the
level on the SCL line low, and starts counting out the width at low level specified in RIICnBRL. When
the RIIC finishes counting out the width at low level, it stops driving the SCL line to the low level (i.e.
releases the line). At this time, if the width at low level of the SCL clock signal from the other master
device is longer than the width at low level set in the RIIC, the width at low level of the SCL signal will
be extended. Once the width at low level for the other master device has ended, the SCL signal rises
because the SCL line has been released. When the RIIC finishes outputting the low-level period of the
SCL clock, the SCL line is released and the SCL clock rises. That is, in cases of contention of SCL
signals from more than one master, the width at high level of the SCL signal is synchronized with that
of the clock having the narrower width, and the width at low level of the SCL signal is synchronized
with that of the clock having the broader width. However, such synchronization of the SCL signal is
only enabled when the RIICnFER.SCLE bit is set to 1.
[SCL clock generation]
[SCL synchronization]
RIICnBRH: I
RIICnBRL: I
Figure 18.21
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Compare match
(Counter clear, low-drive start)
RIICnBRH
SCLn
Falling of SCL detected
(Low-level period count start)
Counter clear
Low-level output of
RIICnBRH
other master device
SCLn
RIICnBRL
2
C bus bit rate high-level register (SCL clock high-level period counter)
2
C bus bit rate low-level register (SCL clock low-level period counter)
Generation and Synchronization of the SCL Signal from the RIIC
2
C bus, a collision of SCL signals may arise due to
Rising of SCL detected
(High-level period count start)
RIICnBRH
RIICnBRL
Compare match
(Counter clear, SCLn line released)
Counter clear
RIICnBRH
18. I²C Bus Interface
RIICnBRH
RIICnBRL
Low-level output of
RIICnBRH
other master device
RIICnBRL RIICnBRL
18-64