Data Read Command Setting Register (Drcmr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.5

Data Read Command Setting Register (DRCMR)

DRCMR is a 32-bit register that sets the commands issued in external address space read mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 24 ―
23 to 16 CMD[7:0]
15 to 8 ―
7 to 0 OCMD[7:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
H'03 R/W
All 0 R
H'00 R/W
25 24 23 22 21
- -
0 0 0 0 0
R R R/W R/W R/W
9 8 7 6 5
- -
0 0 0 0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Command
Sets the command.
Reserved
These bits are always read as 0. The write value should always be 0.
Optional Command
Sets the optional command.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
CMD[7:0]
0 0 0 1 1
R/W R/W R/W R/W R/W
4 3 2 1 0
OCMD[7:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
17-12