Timer I/O Control Register (Tior) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. This module has a total of eight
TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2.
TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also
that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit Bit Name
7 to 4 IOB[3:0]
3 to 0 IOA[3:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
IOB[3:0]
Initial value: 0 0
R/W: R/W R/W
Initial
Value R/W Description
0000 R/W I/O Control B0 to B3
Specify the function of TGRB.
See the following tables.
TIORH_0:
TIOR_1:
TIOR_2:
TIORH_3:
TIORH_4:
0000 R/W I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0:
TIOR_1:
TIOR_2:
TIORH_3:
TIORH_4:
5 4 3 2 1
IOA[3:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
Table 10.11
Table 10.13
Table 10.14
Table 10.15
Table 10.17
Table 10.19
Table 10.21
Table 10.22
Table 10.23
Table 10.25
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
10-13