Axi Bus Response Error Status Register 2 (Axirerrst2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.10

AXI Bus Response Error Status Register 2 (AXIRERRST2)

This register indicates occurrence of AXI bus response errors.
Bit:
31
VDC501RRESP
Initial value:
0
R/W: R
Bit:
15
—
Initial value: 0
R/W: R
Bit Bit Name
31, 30 VDC501RR
ESP
[1:0]
29, 28 VDC501BR
ESP
[1:0]
27, 26 VDC502RR
ESP
[1:0]
25 to 20 —
19, 18 VDC504RR
ESP
[1:0]
17 to 0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
VDC501BRESP VDC502RRESP
[1:0] [1:0] [1:0]
0 0 0 0 0
R R R R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
00 R RRESP[1:0] Signals for Video Display Controller 5 IV3-BUS
These bits indicate the RRESP[1:0] signals received by the IV3-BUS of video
display controller 5. The values of these bits are updated when a response error
occurs.
00: OKAY
10: SLVERR
11: DECERR
00 R BRESP[1:0] Signals for Video Display Controller 5 IV1-BUS
These bits indicate the BRESP[1:0] signals received by the IV1-BUS of video
display controller 5. The values of these bits are updated when a response error
occurs.
00: OKAY
10: SLVERR
11: DECERR
00 R RRESP[1:0] Signals for Video Display Controller 5 IV5-BUS
These bits indicate the RRESP[1:0] signals received by the IV5-BUS of video
display controller 5. The values of these bits are updated when a response error
occurs.
00: OKAY
10: SLVERR
11: DECERR
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
00 R RRESP[1:0] Signals for Video Display Controller 5 IV6-BUS
These bits indicate the RRESP[1:0] signals received by the IV6-BUS of video
display controller 5. The values of these bits are updated when a response error
occurs.
00: OKAY
10: SLVERR
11: DECERR
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
— — — — —
0 0 0 0 0
R R R R R
9 8 7 6 5
—
— — — —
0 0 0 0 0
R R R R R
5. LSI Internal Bus
20 19 18 17 16
VDC504RRESP
— — —
[1:0]
0 0 0 0 0
R R R R R
4 3 2 1 0
—
— — — —
0 0 0 0 0
R R R R R
5-23