Riicndrt - I²C Bus Transmit Data Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.14 RIICnDRT — I²C Bus Transmit Data Register
Access: RIICnDRT is a 32-bit readable/writable register.
RIICnDRTL and RIICnDRTH are 16-bit readable/writable registers.
RIICnDRTLL, RIICnDRTLH, RIICnDRTHL, and RIICnDRTHH are 8-bit readable/writable registers.
Address: RIICnDRT: <RIICn_base> + 003C
RIICnDRTL: <RIICn_base> + 003C
RIICnDRTLL: <RIICn_base> + 003C
RIICnDRTHH: <RIICn_base> + 003F
Initial Value: 0000 00FF
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
When RIICnDRT detects a space in the I
that has been written to RIICnDRT to RIICnDRS and starts transmitting data in transmit mode.
The double-buffer structure of RIICnDRT and RIICnDRS allows continuous transmit operation if the
next transmit data has been written to RIICnDRT while the RIICnDRS data is being transmitted.
RIICnDRT can always be read and written. Write transmit data to RIICnDRT once when a transmit
data empty interrupt (INTRIICTI) request is generated. When writing to bits 8 to 15, be sure to write 0
to these bits.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnDRTH: <RIICn_base> + 003E
H
, RIICnDRTLH: <RIICn_base> + 003D
H
H
This register is initialized by any reset.
H
28 27 26 25
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
H
, RIICnDRTHL: <RIICn_base> + 003E
H
24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— —
0 0 1 1
R R R/W R/W
2
C bus shift register (RIICnDRS), it transfers the transmit data
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
DRT[7:0]
1 1 1 1
R/W R/W R/W R/W
,
H
17 16
— —
0 0
R R
1 0
1 1
R/W R/W
18-41