Reception; Selection Of High-Level Pulse Width - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.12.3

Reception

In reception with the IRDA function enabled, IR frame data from the SCI_RXD0 pin are converted to serial data and
output to the RXD pin for the SCI. When the IRRXINV bit is 0, a bit with the value 0 is output on the detection of a high-
level pulse. When no pulse is received during one-bit period, a bit with the value 1 is output. Pulses shorter than the
lower limit (1.41 μs) are not recognized.
15.12.4

Selection of High-Level Pulse Width

Table 15.20 shows the correspondence between the applicable IRCKS[2:0] bit setting (shortest pulse width), operating
frequency P1φ, and bit rate when the pulse width is shortened below (bit rate × 3/16) in transmission.
Table 15.20 IRCKS[2:0] Bit Setting
2400
P1φ (MHz) 78.13
50 111
64 111
66.67 111
Note 1. The bit rate cannot be set at the SCI.
Note 2. A pulse width shorter than (bit rate × 3/16) cannot be set.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit Rate (bps) (Upper Row) / Bit Cycle × 3/16 (μs) (Lower Row)
9600 19200
19.53 9.77
111 111
111 111
111 111
15. Serial Communications Interface
38400 57600
4.88 3.26
111 111
111 111
111 111
115200
1.63
1
—*
2
—*
2
—*
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