Dma Transfer End Output Function; Dma Transfer End Interrupt - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
• In the write active mode (REQD = 1), DACK0 remains active from the time when a write request is output until one
cycle after the response to the final data is returned.
• When level detection is selected for DREQ0, DREQ0 remains disabled until the cycle following the end of the bus
cycle.
The following signals trigger the rise and fall of DACK0:
Rise: Transfer start (MAWVALID = 1)
Fall: Transfer end (MBVALID & MBREADY = 1)
9.7.6

DMA Transfer End Output Function

TEND0 is a transaction completion signal that is sent to the source of a DMA transfer request. TEND0 is asserted as the
same time as DACK0 for the last transfer transaction. Figure 9.23 shows the TEND0 output timing.
CKIO
Bus cycle
DREQ0
DACK0
TEND0
Figure 9.23 TEND0 Output Timing
9.7.7

DMA Transfer End Interrupt

The DMA transfer end interrupt is an interrupt request signal that indicates that a DMA transaction is completed.
There is an independent DMA transfer end interrupt for each channel.
When the transfer of data equivalent to the total transfer byte count loaded to the CRTB (Current Transaction Byte) is
completed, 1 is set in END of the CHSTAT_n register. In this case, when 0 is set in DEM of the CHCFG_n register, the
DMA transfer end interrupt is output (n = 0 to 15). (When writeback is performed in link mode, the signal is output after
the writeback operation.)
When 0 is set in LV of the header in the read descriptor in link mode, 1 is set in DER of the CHSTAT_n register. In this
case, when 0 is set in DIM of the header, the DMA transfer end interrupt is output.
Table 9.20 Assertion Conditions of DMA Transfer End Interrupt
Source Condition
DMA transaction end When the transfer of data equivalent to the total transfer byte
count loaded to the CRTB (Current Transaction Byte) is
completed with an OKAY response (or after the writeback
operation when writeback is performed in link mode)
Descriptor invalid When 0 is set in LV of the header in the read descriptor in link
mode while 0 is set in DIM of the header
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Last DMA transfer
DMA CPU DMA CPU
9. Direct Memory Access Controller
CPU
DMA Transfer End Interrupt Mask
Signal
DEM bit of the CHCFG_n register
DIM bit of the header
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