Rscan0Thlccm - Transmit History Configuration And Control Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.57 RSCAN0THLCCm — Transmit History Configuration and Control Register
(m = 0 or 1)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0400
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.76
Bit Position
31 to 11
10
9
8
7 to 1
0
THLDTE Bit
When this bit is set to 0, the transmit history data of messages transmitted from transmit/receive FIFO
buffers and the transmit queue is stored in the transmit history buffer. When this bit is set to 1, the
transmit history data of messages transmitted from transmit buffers, transmit/receive FIFO buffers, and
the transmit queue is stored in the transmit history buffer.
Modify this bit only in channel reset mode.
THLIM Bit
This bit is used to select a transmit history interrupt source.
Modify this bit only in channel reset mode.
THLIE Bit
When the THLIE bit is set to 1 and the source selected by the THLIM bit has occurred, a transmit
history interrupt request is generated. Modify the THLIE bit only when the THLE bit set to 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0004 )
H H
28 27 26 25
— — — —
0 0 0 0
R R R R
12 11 10 9
— — THLDTE THLIM
0 0 0 0
R R R/W R/W
RSCAN0THLCCm register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
THLDTE Transmit History Target Buffer Select
0: Entry from transmit/receive FIFO buffers and transmit queue
1: Entry from transmit buffers, transmit/receive FIFO buffers, and transmit
queue
THLIM Transmit History Interrupt Source Select
0: When 12 sets of data have been stored in the transmit history buffer
1: When a single set of transmit history data has been stored
THLIE Transmit History Interrupt Enable
0: Transmit history interrupt is disabled.
1: Transmit history interrupt is enabled.
Reserved These bits are always read as 0. The write value should always be 0.
THLE Transmit History Buffer Enable
0: Transmit history buffer is not used.
1: Transmit history buffer is used.
24 23 22 21
— — — —
0 0 0 0
R R R R
8 7 6 5
THLIE — — —
0 0 0 0
R/W R R R
21. CAN Interface
20 19 18 17
— — — —
0 0 0 0
R R R R
4 3 2 1
— — — —
0 0 0 0
R R R R
16
—
0
R
0
THLE
0
R/W
21-105