Receive Data Sampling Timing And Reception Margin In Asynchronous Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.3.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Since receive data is sampled at the rising edge of the 8th pulse*
bit, as shown in Figure 15.3. Thus the reception margin in asynchronous mode is determined by formula (1) below.
1
M = (0.5 - ) - (L - 0.5) F -
2N
M: Reception margin
N: Ratio of bit rate to clock (N = 16 when ABCS in SEMR = 0, N = 8 when ABCS in SEMR = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 - 1/(2 x 16)} × 100 (%) = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Note 1. This is an example when the ABCS bit in SEMR is 0. When the ABCS bit is 1, a frequency of 8 times the bit rate
is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock
Internal base clock
Receive data (RXDn)
Synchronization
sampling timing
Data sampling
timing
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
D – 0.5
(1+F)
× 100 [%]
N
16 clock pulses
8 clock pulses
0 7
Start bit
1
of the base clock, data is latched at the middle of each
...
Formula (1)
15 0
D0
15. Serial Communications Interface
1
the bit rate.
7 15 0
D1
15-25