Overview; Functional Overview - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.2

Overview

18.2.1

Functional Overview

Communications format
2
• I
• Master mode or slave mode selectable
• Automatic securing of the various set-up times, hold times, and bus-free times for the transfer rate
Transfer rate
Up to 400 kbps
SCL clock
For master operation, the duty cycle of the SCL clock is selectable in the following range.
0% < Duty cycle < 100%
Issuing and detecting conditions
• Start, restart, and stop conditions are automatically generated.
• Start conditions (including restart conditions) and stop conditions are detected.
Slave address
• Up to three slave-address settings can be made.
• Seven- and ten-bit address formats are supported (along with the use of both at once).
• General call addresses, device ID addresses, and SMBus host addresses are detectable.
Acknowledgement
• For transmission, the acknowledge bit is automatically loaded
– Transfer of the next data for transmission can be automatically suspended on detection of a
• For reception, the acknowledge bit is automatically transmitted
– If a wait between the eighth and ninth clock cycles has been selected, software control of the
Wait function
• In reception, the following periods of waiting can be obtained by holding the clock signal (SCL) at
the low level:
– Waiting between the eighth and ninth clock cycles
– Waiting between the ninth clock cycle and the first clock cycle of the next transfer (WAIT
SDA output delay function
Timing of the output of transmitted data, including the acknowledge bit, can be delayed.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
C bus format or SMBus format
not-acknowledge bit.
value in the acknowledge field in response to the received value is possible.
function)
18. I²C Bus Interface
18-3