Rscan0Gtsc - Global Timestamp Counter Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.10 RSCAN0GTSC — Global Timestamp Counter Register
Access: Can be read in 8-, 16- and 32-bit units
Address: <RSCAN0_base> + 0094
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
0 0 0
Initial value
R/W R R R
Table 21.24
Bit Position
31 to 16
15 to 0
TS[15:0] Bits
When the TS[15:0] bits are read, the read value shows the timestamp counter (16-bit free-running
counter) value at that time. When the SOF is detected, the TS[15:0] value is captured and later stored in
the receive buffer or the FIFO buffer. The timestamp counter is initialized in global reset mode.
The timestamp counter starts and stops counting differently, depending on the count source.
• When the TSSS bit in the RSCAN0GCFG register is 0 (pclk):
The timestamp counter starts counting when the RSCAN module has transitioned to global
operating mode.
This counter stops counting when the RSCAN module has transitioned to global stop mode or
global test mode.
• When the TSSS bit is 1 (CANm bit time clock):
The timestamp counter starts counting when the corresponding channel has transitioned to
channel communication mode.
This counter stops counting when the corresponding channel has transitioned to channel reset
mode or channel halt mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
0 0 0
R R R
RSCAN0GTSC register contents
Bit Name Function
Reserved These bits are always read as 0.
TS[15:0] Timestamp Value
The timestamp counter value can be read.
Counter Value: 0000
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
TS[15:0]
0 0 0 0
R R R R
to FFFF
H H
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
0 0 0 0
R R R R
17 16
— —
0 0
R R
1 0
0 0
R R
21-42