Operation In Clock Synchronous Mode; Clock; Cts And Rts Functions - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.5

Operation in Clock Synchronous Mode

Figure 15.17 shows the data format for clock synchronous serial data communications.
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in
transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added.
In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data
reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is
output, the transmission line holds the last bit output state.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data
can be written during transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
*
Synchronization

clock

Serial data
Don't care
Note 1. Holds a high level except during continuous transfer.
Figure 15.17 Data Format in Clock Synchronous Serial Communications (LSB-First)
15.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected, according to the setting of the CKE[1:0] bits in SCR.
When the SCI is operated on an internal clock, the synchronization clock is output from the SCKn pin. Eight
synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is
held high. However, when only data reception is performed, output of the synchronizing clock signal continues until the
CTS function is enabled and the high level is input on the CTSn# pin, an overflow error occurs, or the RE bit in SCR is
set to 0. When the CTS function is enabled, the synchronous clock signal output is stopped if the CTSn# pin input is high
on completion of the frame reception.
15.5.2

CTS and RTS Functions

In the CTS function, CTSn# pin input is used to control reception/transmission start when the clock source is the internal
clock. Setting the SECR.CTSE bit to 1 enables the CTS function.
When the CTS function is enabled, placing the low level on the CTSn# pin causes reception/transmission to start.
In the RTS function, RTSn# pin output is used to request reception/transmission start when the clock source is an
external synchronizing clock. A low level is output when serial communications become possible. Conditions for output
of the low and high level are shown below.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
One unit of transfer data (character or frame)
1
LSB
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
15. Serial Communications Interface
MSB
Bit 5 Bit 6 Bit 7
Don't care
1
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