Csn Assert Period Expansion - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

CSn Assert Period Expansion

The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in

CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and

HW0. Therefore, a flexible interface to an external device can be obtained. Figure 8.10 shows an example. A Th cycle

and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted,

while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices

with slow writing operations.

CSn Assert Period Expansion

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

Note: * The waveform for DACKn is when active low is specified.

8. Bus State Controller

Rz/a1 series Rz/a1lu series Rz/a1lc series