Read Cache - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.7

Read Cache

This module has a simple built-in read cache. The read cache can be used during external address space read mode and
burst read operation. The read cache is configured with a line size of 64 bits and 16 entries.
Read cache configuration is shown in Figure 17.13.
Entry 0
Entry 1
Entry 15
Figure 17.13 Read Cache Configuration
(1) Address Array
The V bit indicates whether the entry data is valid. When the V bit is 1, the data is valid and when V bit is 0, the data is
invalid.
The tag address bits hold the address used for the serial flash memory. Address bits 32 to 3 are used for the purpose.
Address bits 23 to 3 are enabled when address output is 24 bits and one serial flash memory is connected; and address
bits 24 to 3 are enabled when two serial flash memories are connected.
Address bits 31 to 3 are enabled when address output is 32 bits and one serial flash memory is connected; and address
bits 32 to 3 are enabled when two serial flash memories are connected.
(2) Data Array
It retains the 64-bit read data. Registration in the read cache is performed in line units.
(3) Read Operation
In case of read-hit, data is read from the read cache. In case of read-miss, after the 64 × RBURST (read burst length) data
is read from the serial flash memory and the read cache is updated, the data is returned to the bus master.
(4) Data Replacement
The write pointer is used to update data. In case of read-miss, the RBURST (read burst length) portion data is replaced
starting at the entry specified by the write pointer. In other words, the data is replaced in the storage order of the data.
Whether data is referred to or not will not affect the replacement order of data.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Address array
V Tag address Byte
31 (1 + 30) bits
Data array
Byte
64 bits
17. SPI Multi I/O Bus Controller
Byte
17-39