Spi Mode Ddr Enable Register (Smdrenr) (Rz/A1Lu Only) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.23

SPI Mode DDR Enable Register (SMDRENR) (RZ/A1LU only)

SMDRENR is a 32-bit register that sets SDR or DDR transfer of the address, option data, and transfer data in SPI
operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
-
Initial value:
0
R/W:
R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 9 ―
8 ADDRE
7 to 5 ―
4 OPDRE
3 to 1 ―
0 SPIDRE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/W
All 0 R
0 R/W
All 0 R
0 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- ADDRE - - -
0 0 0 0 0
R R/W R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Address DDR Enable
Sets SDR or DDR transfer of the address.
0: SDR transfer
1: DDR transfer
Reserved
These bits are always read as 0. The write value should always be 0.
Option Data DDR Enable
Sets SDR or DDR transfer of the option data.
0: SDR transfer
1: DDR transfer
Reserved
These bits are always read as 0. The write value should always be 0.
Transfer Data DDR Enable
Sets SDR or DDR transfer of the transfer data.
0: SDR transfer
1: DDR transfer
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
OPDRE - - - SPIDRE
0 0 0 0 0
R/W R R R R/W
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