RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
11.
OS Timer
11.1
Functional Overview
The OS timer has the following features.
• Two operating modes
– Interval timer mode
– Free-running comparison mode
• Choice between startup of DMA by compare match and generation of interrupt
11.1.1
Features of OSTM
Channels
This product has the following number of channels of the OS timer.
Table 11.1
Number of Channels
Name
Meaning of n
Throughout this section, the individual channels of the OS timer are identified by the index "n" (n = 0,
1), for example OSTMnTO for the OS timer n output register.
Register address
The register addresses of the OS timer are given as offsets from the individual base addresses
<OSTMn_base>.
The register base addresses of each OSTMn are listed in the following table.
Table 11.2
Base Address Name
<OSTM0_base>
<OSTM1_base>
Interrupts
The OS timers can generate the following interrupt requests.
Table 11.3
OSTMn Signal
OSTM0TINT
OSTM1TINT
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Channels of OS timer
Register Base Addresses
OSTMn Interrupt Requests
Function
interrupt
OSTM0
interrupt
OSTM1
OS Timer
2
OSTMn
Base Address
FCFE C000
H
FCFE C400
H
Startup of Direct Memory Access Controller
√
√
11. OS Timer
11-1