Serial Control Register (Scscr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.6

Serial Control Register (SCSCR)

SCSCR enables/disables the transmitter/receiver operation and interrupt requests, and selects the transmit/receive clock
source. The CPU can always read and write to SCSCR.
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
—
15 to 8
7 TIE
6 RIE
5 TE
4 RE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested
when the serial transmit data is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), the quantity of data in the
transmit FIFO register becomes less than the specified number of transmission
triggers, and then the TDFE flag in the serial status register (SCFSR) is set to 1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled
1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled*
Note: * The TXI interrupt request can be cleared by writing a greater quantity of
0 R/W Receive Interrupt Enable
Enables or disables the receive FIFO data full (RXI) interrupts requested when
the RDF flag or DR flag in serial status register (SCFSR) is set to 1, receive-
error (ERI) interrupts requested when the ER flag in SCFSR is set to 1, and
break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag
in line status register (SCLSR) is set to 1.
0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break
interrupt (BRI) requests are disabled
1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break
interrupt (BRI) requests are enabled*
Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag
0 R/W Transmit Enable
Enables or disables serial transmission.
0: Serial transmission disabled
1: Serial transmission enabled*
Note: * When this bit is set to 1, serial transmission starts after writing of
0 R/W Receive Enable
Enables or disables serial reception.
0: Serial reception disabled*
1: Serial reception enabled*
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK,
14. Serial Communication Interface with FIFO
9 8 7 6 5
- - TIE RIE TE
0 0 0 0 0
R R R/W R/W R/W
transmit data than the specified transmission trigger number to
SCFTDR and clearing TDFE to 0 after reading 1 from TDFE, or by
clearing TIE to 0.
after it has been set to 1, then clearing the flag to 0, or by clearing RIE
to 0. ERI or BRI interrupt requests can be cleared by reading the ER,
BRK or ORER flag after it has been set to 1, then clearing the flag to 0,
or by clearing RIE and REIE to 0.
transmit data into SCFTDR. Be sure to select the transmit format in
SCSMR and SCFCR and reset the transmit FIFO before setting TE to
1.
1
2
RDF, FER, PER, and ORER). These flags retain their previous
values.
2. When this bit is set to 1, serial reception starts when a start bit is
detected in asynchronous mode, or synchronous clock is
detected in clock synchronous mode. Be sure to select the
receive format in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
4 3 2 1 0
RE REIE - CKE[1:0]
0 0 0 0 0
R/W R/W R R/W R/W
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