Renesas Serial Peripheral Interface; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.

Renesas Serial Peripheral Interface

This LSI circuit includes three independent Renesas serial peripheral interfaces.
This module is capable of full-duplex synchronous serial communication.
16.1

Features

This module has the following features.
• SPI transfer functions
Use of MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (SPI clock) signals
allows for serial communications through SPI operation (four-wire method).
Capable of serial communications in master/slave mode
Supports mode fault error detection (only in SPI slave mode)
Supports overrun error detection (only in SPI slave mode)
Switching of the polarity of the serial transfer clock
Switching of the clock phase of serial transfer
• Data format
MSB-first/LSB-first selectable
Transfer bit-length is selectable as 8, 16, or 32 bits.
• Bit rate
RSPCK can be divided by a maximum of 4096 in master mode
RSPCK can be generated by dividing P1φ by the on-chip baud rate generator.
An externally input clock can be used as a serial clock.
• Buffer configuration
8 bytes for transmission and 32 bytes for reception
• SSL control function
One SSL signal for each channel
In master mode, outputs SSL signal.
In slave mode, inputs SSL signal.
Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable delay from RSPCK stoppage to SSL output negation (SSL negation delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable wait for next-access SSL output assertion (next-access delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Function for changing SSL polarity
• Control in master transfer
A transfer of up to four commands can be executed sequentially in looped execution.
For each command, the following can be set:
SSL signal value, bit rate, RSPCK polarity/phase, transfer data length, LSB/MSB first, burst, RSPCK delay, SSL
negation delay, and next-access delay.
A transfer can be initiated by writing to the transmit buffer.
A transfer can be initiated by clearing the SPTEF bit.
MOSI signal value specifiable in SSL negation
• Interrupt sources
Maskable interrupt sources:
Receive interrupt (receive buffer full)
Transmit interrupt (transmit buffer empty)
Error interrupt (mode fault, overrun)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
16. Renesas Serial Peripheral Interface
16-1