Smart Card Mode Register (Scmr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.8

Smart Card Mode Register (SCMR)

b7 b6
BCP2 —
1 1
Value after reset:
Bit Symbol Bit Name
b0 SMIF Smart Card Interface Mode
Select
b1 — Reserved
b2 SINV Transmitted/Received Data
Invert
b3 SDIR Transmitted/Received Data
Transfer Direction
b6 to b4 — Reserved
b7 BCP2 Base Clock Pulse 2
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
Note 2. S is the value of S in BRR (see section 15.2.9, Bit Rate Register (BRR)).
SMIF Bit (Smart Card Interface Mode Select)
When this bit is set to 1, smart card interface mode is selected.
When this bit is set to 0, asynchronous or clock synchronous mode is selected.
SINV Bit (Transmitted/Received Data Invert)
Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity
bit, invert the PM bit in SMR.
SDIR Bit (Transmitted/Received Data Transfer Direction)
Selects the serial/parallel conversion format.
BCP2 Bit (Base Clock Pulse 2)
Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in
combination with the SMR.BCP[1:0] bits.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
— — SDIR SINV
1 1 0 0
Description
0: Serial communications interface mode
1: Smart card interface mode
This bit is read as 1. The write value should be 1.
0: TDR contents are transmitted as they are. Receive data is stored as
it is in RDR.
1: TDR contents are inverted before being transmitted. Receive data is
stored in inverted form in RDR.
0: Transfer with LSB-first
1: Transfer with MSB-first
This bit is read as 1. The write value should be 1.
Selects the number of base clock cycles in combination with the
SMR.BCP[1:0] bits.
Setting values in the SCMR.BCP2 bit and SMR.BCP[1:0] bits
BCP2 BCP1 BCP0
0
0
0
0
1
1
1
1
b1 b0
— SMIF
1 0
0 0: 93 clock cycles (S = 93)*
0 1: 128 clock cycles (S = 128)*
1 0: 186 clock cycles (S = 186)*
1 1: 512 clock cycles (S = 512)*
0 0: 32 clock cycles (S = 32)*
0 1: 64 clock cycles (S = 64)*
1 0: 372 clock cycles (S = 372)*
1 1: 256 clock cycles (S = 256)*
15. Serial Communications Interface
2
2
2
2
2
(Initial Value)
2
2
2
R/W
1
R/W*
R
1
R/W*
1
R/W*
R
1
R/W*
15-16