Dma Transfer; Transfer Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.7

DMA Transfer

The basic operation of DMA transfer is described here.
9.7.1

Transfer Mode

Two transfer modes are supported: single transfer mode and block transfer mode.
To select a transfer mode, set the TM bit of CHCFG_n for each channel.
Table 9.16 Basic Transfer Setting
TM
Transfer Mode (CHCFG_n)
Single transfer 0
Block transfer 1
(1) Single Transfer Mode
When a DMA transfer request is received, a DMA transfer is executed once in the direction indicated by REQD (source
or destination). A DMA transfer is executed once each time a transfer request is received, and this operation continues
until the number of bytes loaded to CRTB_n is reached (arbitration between channels is accomplished for each DMA
transfer).
DREQ0
DACK0
DMA Transfer
Figure 9.11 Single Transfer Mode (REQD = 1, SDS > DDS)
(2) Block Transfer Mode
Once a DMA transfer request is received, the DMAC continues to execute the transfer until data equivalent to the
number of bytes loaded to the DMA transfer byte register (CRTB_n register) is transferred (the DMA transaction is
completed) (arbitration between channels is accomplished for each DMA transfer).
DREQ0
DACK0
DMA Transfer
Figure 9.12 Block Transfer Mode (REQD = 0, SDS < DDS)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Function
A single DMA transfer is executed in response to a DMAREQ.
In response to a DMAREQ, the DMAC continues to execute the transfer until the DMA
transaction is completed.
Write
Read Write
Read Write
9. Direct Memory Access Controller
Write Write
Read Write
9-52