Channel Control Register N (Chctrl_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.8

Channel Control Register n (CHCTRL_n)

This register controls the DMA transfer operation on DMA channel n (n = 0 to 15).
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
0
Initial value:
R/W:
R
Bit Bit Name
31 to 18 —
17 CLRINTMSK
16 SETINTMSK
15 to 10 —
9 CLRSUS
8 SETSUS
7 —
6 CLRTC
5 CLREND
4 CLRRQ
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved area. Set 0. A read operation results in 0 being read.
0 R/W When this bit is set to 1, the mask of the DMA transfer end interrupt is cleared. Also,
the INTMSK bit of the CHSTAT_n register is set to 0.
If the mask is cleared when 1 is set in both LVINT of the DCTRL register and END of
the CHSTAT_n register, the DMA transfer end interrupt becomes active. (It does not
become active when 0 is set in LVINT.)
A read operation results in 0 being read.
1: Clears the mask set by SETINTMSK.
0: Does not affect the operation.
0 R/W When this bit is set to 1, the DMA transfer end interrupt is temporarily masked. Also,
the INTMSK bit of the CHSTAT_n register is set to 1.
A read operation results in 0 being read.
1: Masks the DMA transfer end interrupt.
0: Does not affect the operation.
All 0 R Reserved area. Set 0. A read operation results in 0 being read.
0 R/W Clear Suspend
Clears the suspend status. Setting this bit to 1 when 1 is set in SUS of the CHSTAT_n
register can clear the suspend status.
An attempt to read this bit results in 0 being read.
1: Clears the suspend status of the current DMA transfer.
0: Does not affect the operation.
0 R/W Set Suspend
Suspends the current DMA transfer. Setting this bit to 1 when 1 is set in EN of the
CHSTAT_n register can suspend the current DMA transfer.
An attempt to read this bit results in 0 being read.
1: Suspends the current DMA transfer.
0: Does not affect the operation.
0 R Reserved area. Set 0. A read operation results in 0 being read.
0 R/W Clear TC bit
Setting this bit to 1 can clear the TC bit of the CHSTAT_n register. An attempt to read
this bit results in 0 being read.
1: Clears the TC bit.
0: Does not affect the operation.
0 R/W Clear End bit
Setting this bit to 1 can clear the END bit of the CHSTAT_n register.
Also, the DMA transfer end interrupt is cleared.
An attempt to read this bit results in 0 being read.
1: Clears the END bit.
0: Does not affect the operation.
0 R/W Clear Request bit
Setting this bit to 1 can clear the RQST bit of the CHSTAT_n register.
An attempt to read this bit results in 0 being read.
1: Clears the RQST bit.
0: Does not affect the operation.
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
CLR SET CLR
- CLRTC
SUS SUS END
0 0 0 0 0
R/W R/W R R/W R/W
9. Direct Memory Access Controller
20 19 18 17 16
CLRINT SETINT
- - -
MSK MSK
0 0 0 0 0
R R R R/W R/W
4 3 2 1 0
CLRRQ SWRST STG CLREN SETEN
0 0 0 0 0
R/W R/W R/W R/W R/W
9-18