Next Source Address Register N (N0Sa_N, N1Sa_N); Next Destination Address Register N (N0Da_N, N1Da_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.1

Next Source Address Register n (N0SA_n, N1SA_n)

This register sets the DMA transfer source address (32 bits) of DMA channel n (n = 0 to 15) which is to be executed next.
N0SA_n is for the Next0 Register Set, and N1SA_n is for the Next1 Register Set.
In register mode, set this register set by using software. In link mode, the descriptor read data is automatically set in the
Next0 Register Set.
These register set values are loaded to the Current Register Set and used for DMA transfer.
Bit:
31
Initial value:
0
R/W:
R/W
Bit:
15
0
Initial value:
R/W:
R/W
Initial
Bit Bit Name Value
31 to 0 SA All 0
9.4.2

Next Destination Address Register n (N0DA_n, N1DA_n)

This register sets the DMA transfer destination address (32 bits) of DMA channel n (n = 0 to 15) which is to be executed
next.
N0DA_n is for the Next0 Register Set, and N1DA_n is for the Next1 Register Set.
In register mode, set this register set by using software. In link mode, the descriptor read data is automatically set in the
Next0 Register Set.
These register set values are loaded to the Current Register Set and used for DMA transfer.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
0
Initial value:
R/W: R/W
Initial
Bit Bit Name Value
31 to 0 DA All 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
R/W Description
R/W Source Address
Sets the start address of the DMA transfer source.
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
R/W Description
R/W Destination Address
Sets the start address of the DMA transfer destination.
25 24 23 22 21
SA
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
SA
0 0 0 0 0
R/W R/W R/W R/W R/W
25 24 23 22 21
DA
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
DA
0 0 0 0 0
R/W R/W R/W R/W R/W
9. Direct Memory Access Controller
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
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