Secondary Cache; Features; Configuration Signals - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
4.

Secondary Cache

This product incorporates Arm's PL310 as a secondary cache. The IP version is r3p2.
4.1

Features

• Total cache size:
• Number of cache ways:
• Number of master ports :
• Number of slave ports:
• Lockdown by master:
• Lockdown by line
• Speculative read:
• Sideband signal from CA9:
For details, see CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference Manual issued by Arm Ltd.
4.2

Configuration Signals

The setting values of the configuration signals are shown in Table 4.1.
Table 4.1 Setting Values of Configuration Signals
Configuration Signals
1
ASSOCIATIVITY*
CACHEID[5:0]
1
CFGADDRFILTEN*
CFGADDRFILTEND[11:0]*
CFGADDRFILTSTART[11:0]*
CFGBIGEND
1
DATAREADLAT[2:0]*
1
DATASETUPLAT[2:0]*
1
DATAWRITELAT[2:0]*
2
REGFILEBASE[19:0]*
1
TAGREADLAT[2:0]*
1
TAGSETUPLAT[2:0]*
1
TAGWRITELAT[2:0]*
1
WAYSIZE[2:0]*
Note 1. Do not change the initial settings of these signals by software.
Note 2. The base address for the PL310 registers is H'3FFFF000. For the details and overview of the registers, see CoreLink™ Level 2
Cache Controller L2C-310 Technical Reference Manual issued by Arm Ltd. The external ROM/RAM mirror area (0x4000_0000
to 0x5FFF_FFFF) is mirrored before the secondary cache. Accordingly, when a cache maintenance operation is to be executed
for the external ROM/RAM mirror area, treat this as the normal external ROM/RAM area in the physical addresses range from
0x0000_0000 to 0x1FFF_FFFF.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
128 Kbytes
8 ways
2
2
No
Defined
No
No
1
1
Setting Values
1'b0 (8 ways)
6'b000000
1'b1
12'h3FF
12'h180
1'b0
3'b000
3'b000
3'b000
20'h3FFFF
3'b000
3'b000
3'b000
3'b001 (16 Kbytes)
4. Secondary Cache
4-1