Channel Modes - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.5.2

Channel Modes

Figure 21.5 shows a channel mode state transition chart. Table 21.86 shows the channel mode
transition time.
This LSI reset
Channel stop mode
CSLPR = 0
Channel reset mode
CHMDC[1:0] = 00
B
SOF
detected
CHMDC[1:0], CSLPR, BOM[1:0]: Bits in the RSCAN0CmCTR register (m = 0 or 1)
BOSTS, TRMSTS, RECSTS, COMSTS: Bits in the RSCAN0CmSTS register
Note 1. Timing of transition from bus off state to channel halt mode
- When BOM[1:0] = 01
- When BOM[1:0] = 10
- When BOM[1:0] = 11
Note 2. While the CAN bus is locked at the dominant level, transition to channel halt mode is not made. In that case, enter channel
reset mode.
Figure 21.5
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
CSLPR = 1
CHMDC[1:0] = 10
CHMDC[1:0] = 01
CHMDC[1:0] = 01
B
Channel communication mode
Reception
Arbitration lost
BOSTS = 0
TRMSTS = 0
RECSTS = 1
COMSTS = 1
Reception
completed
Idle
BOSTS = 0
TRMSTS = 0
RECSTS = 0
11 consecutive recessive bits
COMSTS = 1
have been detected 128 times
(BOM[1:0] bits are set to 00
: Transition to channel halt mode when TEC exceeds 255
B
: Transition to channel halt mode when 11 consecutive recessive bits have been detected 128 times
B
: Transition to channel halt mode when the CHMDC[1:0] bits are set to 10
B
Channel Mode State Transition Chart
B
Channel halt mode
B
CHMDC[1:0] = 00 CHMDC[1:0] = 10
B
Transmission
BOSTS = 0
TRMSTS = 1
RECSTS = 0
COMSTS = 1
11 consecutive recessive
bits have been detected
128 times (BOM[1:0] bits
are set
to 00 ) and transmission
B
TEC > 255
start
Bus off
BOSTS = 1
TRMSTS = 1
RECSTS = 0
COMSTS =1
)
B
21. CAN Interface
B
2
*
1
*
B
21-121