Operation; Overview Of Operations - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.4

Operation

In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the
final valid data.
16.4.1

Overview of Operations

This module is capable of serial transfers in slave mode and master mode. A particular mode of this module can be
selected by using the MSTR bit in the control register (SPCR). Table 16.4 gives the relationship between the modes and
SPCR settings, and a description of each mode.
Table 16.4 Relationship between Modes and SPCR and Description of Each Mode
Mode
MSTR bit setting
MODFEN bit setting
RSPCK signal
MOSI signal
MISO signal
SSL signal
SSL polarity modification function
Transfer rate
Clock source
Clock polarity
Clock phase
First transfer bit
Transfer data length
Burst transfer
RSPCK delay control
SSL negation delay control
Next-access delay control
Transfer activation method
Sequence control
Transmit buffer empty detection
Receive buffer full detection
Overrun error detection
Mode fault error detection
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Slave (SPI Operation)
0
0 or 1
Input
Input
Output/Hi-Z
Input
Supported
Up to P1 φ /8
RSPCK input
Two
Two
MSB/LSB
8, 16, or 32 bits
Possible (CPHA = 1)
Not supported
Not supported
Not supported
SSL input active or RSPCK oscillation
Not supported
Supported
Supported
Supported
Supported (MODFEN = 1)
16. Renesas Serial Peripheral Interface
Master (SPI Operation)
1
0
Output
Output
Input
Output
Supported
Up to P1 φ /2
On-chip baud rate generator
Two
Two
MSB/LSB
8, 16, or 32 bits
Possible (CPHA = 0,1)
Supported
Supported
Supported
Transmit buffer is written when SPE = 1
Supported
Supported
Supported
Not Supported
Not supported
16-20