Tend0 Not Output; Atomic Access (Arlock[1:0] And Awlock[1:0]) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.9.2

TEND0 Not Output

Note that TEND0 may not be output depending on the combination of the bits DDS[3:0], SDS[3:0] and REQD in the
CHCFG_0 register.
Table 9.30 shows when TEND0 is not output and Figure 9.39 shows an operation example.
Table 9.30 Bit Combination when TEND0 Is Not Output
CHCFG_0 Register
REQD DDS
1 —
0 DDS > SDS
DDS = SDS
DDS < SDS
CKIO
CHCFG_0
REQD
DDS[3:0] 0
SDS[3:0]
2
DACK0
TEND0
DMA Transfer
Figure 9.39 TEND0 Not Output
9.9.3

Atomic Access (ARLOCK[1:0] and AWLOCK[1:0])

This module does not support atomic (locked or exclusive) access, that is, it only supports normal access.
Signals ARLOCK[1:0] and AWLOCK[1:0] are fixed as follows and cannot be modified.
ARLOCK[1:0], AWLOCK[1:0]: 00 (normal access)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
SDS
—
Read Read
9. Direct Memory Access Controller
TEND0 Output
Output
Output
Output
Not output
TEND0 is not output
Read Read Write Write
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