Control Register (Spcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.1

Control Register (SPCR)

SPCR sets the operating mode. If the MSTR and MODFEN bits are changed while the function of this module is enabled
by setting the SPE bit to 1, subsequent operations cannot be guaranteed.
Bit Bit Name
7 SPRIE
6 SPE
5 SPTIE
4 SPEIE
3 MSTR
2 MODFEN
1, 0 ―
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
SPRIE SPE SPTIE SPEIE MSTR
Initial value: 0 0 0
R/W: R/W R/W R/W
Initial Value R/W Function
0 R/W Receive Interrupt Enable
Enables or disables generation of receive interrupt requests (SPRI) when
the number of receive data units in the receive buffer (SPRX) is equal to
or greater than the specified receive buffer data triggering number and
the SPRF flag in SPSR is set to 1.
0: Disables the generation of receive interrupt requests.
1: Enables the generation of receive interrupt requests.
0 R/W Function Enable
Setting this bit to 1 enables the module function. When the MODF bit in
the status register (SPSR) is 1, the SPE bit cannot be set to 1 (see
section 16.4.6, Error Detection). Setting the SPE bit to 0 disables the
module function, and initializes a part of the module function (see section
16.4.7, Initialization).
0: Disables the module function.
1: Enables the module function.
0 R/W Transmit Interrupt Enable
Enables or disables generation of transmit interrupt requests (SPTI) when
the number of transmit data units in the transmit buffer (SPTX) is equal to
or less than the specified transmit buffer data triggering number and the
SPTEF flag in SPSR is set to 1.
0: Disables the generation of transmit interrupt requests.
1: Enables the generation of transmit interrupt requests.
0 R/W Error Interrupt Enable
Enables or disables the generation of error interrupt requests when this
module detects a mode fault error and sets the MODF bit in the status
register (SPSR) to 1, or when this module detects an overrun error and
sets the OVRF bit in SPSR to 1 (see section 16.4.6, Error Detection).
0: Disables the generation of error interrupt requests.
1: Enables the generation of error interrupt requests.
Note: This bit is valid only in SPI slave mode.
0 R/W Master/Slave Mode Select
Selects master/slave mode. According to MSTR bit settings, this module
determines the direction of the RSPCK, MOSI, MISO, and SSL pins.
0: Slave mode
1: Master mode
0 R/W Mode Fault Error Detection Enable
Enables or disables the detection of a mode fault error (see section
16.4.6, Error Detection).
0: Disables the detection of a mode fault error.
1: Enables the detection of a mode fault error.
Note: This bit is valid only in SPI slave mode. When master mode is
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
16. Renesas Serial Peripheral Interface
4 3 2 1 0
MOD ⎯ ⎯
FEN
0 0 0 0 0
R/W R/W R/W R R
specified with the MSTR bit, this bit should always be cleared to 0.
16-6