Others - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.5.11

Others

(1) Reset
This module can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data
output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal
clock. All control registers are initialized. In software standby and sleep, control registers of the bus state controller are
not initialized.
(2) Caution on Write Buffer
Since the bus state controller incorporates a one-stage write buffer, it can execute an access via the internal bus before the
previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-
speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory
write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after
the data write to the device has been completed, perform a dummy read to the same address to check for completion of
the write before the next process to be executed.
The write buffer of the bus state controller functions in the same way for an access by a bus master other than the CPU
such as the direct memory access controller. Accordingly, to perform DMA transfers, the next read cycle is initiated
before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist
in external memory space, the next read cycle will not be initiated until the previous write cycle is completed.
Changing the registers in this module while the write buffer is operating may disrupt correct write access. Therefore, do
not change the registers in this module immediately after a write access. If this change becomes necessary, do it after
executing a dummy read of the write data.
(3) On-Chip Peripheral Module Access
To access an on-chip module register, two or more peripheral module clock (P0
When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without
waiting for the completion of writing to registers.
For example, a case is described here in which the system is transferring to the software standby mode for power savings.
To make this transition, the WFI instruction must be performed after setting the STBY bit in the STBCR1 register to 1.
However a dummy read of the STBCR1 register is required before executing the WFI instruction. If a dummy read is
omitted, the CPU executes the WFI instruction before the STBY bit is set to 1, thus the system enters sleep mode not
software standby mode. A dummy read of the STBCR1 register is indispensable to complete writing to the STBY bit.
To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy
read of registers to which write instruction is given and then perform the succeeding instructions.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
8. Bus State Controller
ϕ ϕ
or P1 ) cycles are required.
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