Transmit Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
(1) Configuration Mode
This mode is entered after the module is released from reset. All required configuration fields in the control register
should be defined in this mode, before this module is enabled by setting the TEN and REN bits.
Setting the TEN and REN bits causes the module to enter the module enabled mode.
(2) Module Enabled Mode
Operation of the module in this mode is dependent on the operation mode selected. For details, refer to section 19.4.6,
Transmit Operation, and section 19.4.7, Receive Operation, below.
19.4.6

Transmit Operation

Transmission can be controlled either by DMA transfer or interrupt.
DMA control is preferred to reduce the processor load. In DMA control mode, the processor will only receive interrupts
if there is an underflow or overflow of data or if the DMA transfer has been completed.
The alternative method is using the interrupts that this module generates to supply data as required.
When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit indicates that the module
is in the idle state.
Figure 19.23 shows the transmit operation in DMA control mode, and Figure 19.24 shows the transmit operation in
interrupt control mode.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
19. Serial Sound Interface
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