Control Register 2 (Rcr2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
13.3.17

Control Register 2 (RCR2)

RCR2 is a register for periodic interrupt control, 30-second adjustment, divider circuit RESET, and count control.
RCR2 is initialized by a power-on reset or in deep standby mode. The RTCEN bit is only initialized by a power-on reset
using the RES pin.
Bit Bit Name
7 PEF
6 to 4 PES[2:0]
3 RTCEN
2 ADJ
1 RESET
0 START
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
BIt: 7 6
PEF PES[2:0]
Initial value: 0 0
R/W: R/W R/W
Initial
Value R/W Description
0 R/W Periodic Interrupt Flag
Indicates that an interrupt is generated with the period designated by the PES2
to PES0 bits. When set to 1, PEF generates periodic interrupts.
0: Interrupts not generated with the period designated by the bits PES2 to PES0.
[Clearing condition]
When 0 is written to PEF
1: Interrupts generated with the period designated by the PES2 to PES0 bits.
[Setting condition]
When an interrupt is generated with the period designated by the bits PES0 to
PES2 or when 1 is written to the PEF flag
000 R/W Interrupt Enable Flags
These bits specify the period of the periodic interrupt.
000: No periodic interrupts generated
001: Setting prohibited
010: Periodic interrupt generated every 1/64 second
011: Periodic interrupt generated every 1/16 second
100: Periodic interrupt generated every 1/4 second
101: Periodic interrupt generated every 1/2 second
110: Periodic interrupt generated every 1 second
111: Periodic interrupt generated every 2 seconds
1 R/W RTC_X1 Clock Control
Controls the function of the RTC_X1 pin.
0: Halts the on-chip crystal oscillator/disables the external clock input.
1: Runs the on-chip crystal oscillator/enables the external clock input.
Note: The on-chip crystal oscillator selected with the RCKSEL[1:0] bits in the
RCR5 register runs. This bit must not be set to 1 when the RCKSEL[1:0] bits are
set to 01.
0 R/W 30-Second Adjustment
When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded
down to 00 seconds and 30 seconds or more up to 1 minute. The divider circuit
(prescaler and R64CNT) will be simultaneously reset. The ADJ bit is
automatically reset to 0; there is no need to write 0 to this bit. This bit is always
read as 0.
0: Normal clock operation
1: 30-second adjustment
0 R/W Reset
Writing 1 to this bit initializes the divider circuit, the R64CNT register, the alarm
register, the RCR3 register, bits CF and AF in RCR1, and bit PEF in RCR2. In
this case, the RESET bit is automatically reset to 0 after 1 is written to and the
above registers are reset. Thus, there is no need to write 0 to this bit. This bit is
always read as 0.
0: Normal clock operation
1: Divider circuit is reset.
1 R/W Start
Halts and restarts the counter (clock).
0: Second, minute, hour, day, week, month, and year counters halt.
1: Second, minute, hour, day, week, month, and year counters run normally.
5 4 3 2 1
RTCEN ADJ RESET START
0 0 1 0 0
R/W R/W R/W R/W R/W
13. Realtime Clock
0
1
R/W
13-13