Setting Example 2 (Register Mode/Software Request) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.8.2

Setting Example 2 (Register Mode/Software Request)

The following table shows a setting example applicable when DMA transfer is executed using the settings shown below.
Table 9.23 DMA Transfer Setting Example 2
Item
Channel used
Priority control
DMA mode
Transfer mode
Register set used
Source/destination
Start address
Address direction
Data size
DMA transfer byte count
DMA transfer request
DMAACK signal
DMA transfer end interrupt mask
CACHE setting
Setting example 2
DCTRL = 0000_0001H (DMA setting)
N1SA = 0FFF_E000H (source address)
N1DA = 3333_0000H (destination address)
N1TB = 0000_0080H (transfer byte count)
CHCFG = 1045_0402H (configuration)
CHITVL = 0000_0000H (interval)
CHEXT = 0000_0000H (CACHE setting)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Description
2
Round robin
Register
Block transfer
Next1
Source
0FFF_E000H
Increment
8 bits
128 bytes
Auto request
Masked
Not masked
Default value
9. Direct Memory Access Controller
Destination
3333_0000H
Increment
256 bits
9-68