Issuing A Stop Condition - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.12.3

Issuing a Stop Condition

The RIIC issues a stop condition when the RIICnCR2.SP bit is set to 1.
When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop
condition when the RIICnCR2.BBSY flag is 1 (bus busy) and the RIICnCR2.MST bit is 1 (master
mode).
A stop condition is issued in the following sequence.
[Stop condition issuance]
• Drive the SDA line low (high level to low level).
• Ensure the low-level period of SCL line set in RIICnBRL.
• Release the SCL line (low level to high level).
• Detect a high level of the SCL line and ensure the time set in RIICnBRH and the stop condition
setup time.
• Release the SDA line (low level to high level).
• Ensure the time set in RIICnBRL and the bus free time.
• Clear the BBSY flag to 0 (to release the bus mastership).
SCLn
SDAn
IICφ
BBSY
MST
TRS
TDRE
STOP
SP
Figure 18.38
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
RIICnBRL RIICnBRH RIICnBRL
8
b0
Stop Condition Issue Timing (SP Bit)
RIICnBRH RIICnBRL
9
ACK/NACK
Accept stop condition issuance
Write 1 to SP
18. I²C Bus Interface
Setup time Bus free time
RIICnBRH RIICnBRL
P
Issue stop
condition
Clear STOP to 0
18-83