Functional Description-Transmitter; Transmitter Module; Transmitter Module Initialization - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.8 Functional Description—Transmitter
23.8.1

Transmitter Module

The transmitter module transmits PCM data and auxiliary information after encoding it according to the method of
biphase-mark modulation that complies with the IEC60958 standard (SPDIF).
The clock for the transmitter module is an oversampling clock supplied from the outside. This clock usually selects a
value that serves as an oversample at a frequency eight times larger than the clock frequency required for biphase-mark
encoding. In this case, the clock frequency required to transmit 32 time slots in a subframe is 512 times as large as the
sample frequency for audio data.
Audio data and channel status information are first written into the module's channel 1 and then into channel 2.
Generally, the channel status need to be written only when the information changes. The SPDIF module requests that the
channel status be written in 30 frames -- when all the current channel status data have been transmitted. You need to write
somewhere between frame 31 and the beginning of the next block of 192 frames.
The audio data is stored in a double buffer arrangement. To make sure that the first stage buffer is empty, you can send an
interrupt request or poll the status register. DMA transfers send channel 1 audio data on the first request and channel 2
data on the second.
The channel status information is stored in the 30-bit registers of channels 1 and 2. For each channel, the channel status
information per frame consists of 192 bits. Because necessary data covers only 30 bits, zeros continue to be sent after the
transmission of the first 30 bits until the block is completed.
User data forms a 32-bit double buffer arrangement. You can make sure that the first stage buffer is empty by either
sending an interrupt request or polling the status register. Usually, information about the user data will become
insufficient with the length of data between blocks. Transmission takes place in a sequence of channels 1 and 2. For the
user data within a block, 384 bits are transmitted before the next block is continuously transmitted.
The audio data handled by the Renesas SPDIF module is a linear PCM, making it possible to set up to 24 bits. For this
reason, the V flag indicating that audio data is a linear PCM remains to be 0. The V flag involves no register-based
setting. An even parity is created for each 32 bits of serial output data (excluding the preamble).
Note: • When transmitter user buffer underrun occurs, the current data in the buffer data of SPDIF is transmitted until the
next data is filled.
23.8.2

Transmitter Module Initialization

The device defaults to an idle state when it comes out of reset, or can be put into an idle state when 0 is written to the
TME bit in the CTRL register. When the transmitter module is idle, it has the following settings:
• The transmitter idle status bit (TIS) is set to 1, all other status bits are cleared to 0.
• Preamble generation is invalid.
• Synchronization between channels 1 and 2 is set to 0 (0 for channel 1, 1 for channel 2).
• Both word_count and frame_count are set to 0.
• The output from the biphase-mark encoder is set to 0.
Channel status, user and audio data registers will retain its value prior to putting the module into idle. To exit the idle
state the user must write 1 to the TME bit in the CTRL register.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
23. Renesas SPDIF Interface
23-21