Rscan0Txqccm - Transmit Queue Configuration And Control Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.54 RSCAN0TXQCCm — Transmit Queue Configuration and Control Register
(m = 0 or 1)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 03A0
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — TXQIM TXQIE
0 0 0
Initial value
R/W R R R/W
Table 21.73
Bit Position
31 to 14
13
12
11 to 8
7 to 1
0
TXQIM Bit
This bit is used to select a transmit queue interrupt source. Modify this bit in channel reset mode.
TXQIE Bit
When the TXQIE bit is set to 1 and the source selected by the TXQIM bit occurs, an interrupt request is
generated.
Set the TXQE bit to 0 before modifying the TXQIE bit.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0010 )
H H
28 27 26 25
— — — —
0 0 0 0
R R R R
12 11 10 9
TXQDC[3:0]
0 0 0 0
R/W R/W R/W R/W
RSCAN0TXQCCm register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
TXQIM Transmit Queue Interrupt Source Select
0: When the buffer becomes empty upon completion of message
transmission, a transmit queue interrupt request is generated.
1: A transmit queue interrupt request is generated each time a message has
been transmitted.
TXQIE Transmit Queue Interrupt Enable
0: Transmit queue interrupt is disabled.
1: Transmit queue interrupt is enabled.
TXQDC[3:0] Transmit Queue Depth Configuration
Setting these bits to g (g = 2 to 15) makes the (g + 1)-buffer transmit queue
available.
Setting these bits to 0 disables the transmit queue.
Setting these bits to 1 is prohibited.
Reserved These bits are always read as 0. The write value should always be 0.
TXQE Transmit Queue Enable
0: The transmit queue is not used.
1: The transmit queue is used.
24 23 22 21
— — — —
0 0 0 0
R R R R
8 7 6 5
— — —
0 0 0 0
R/W R R R
21. CAN Interface
20 19 18 17
— — — —
0 0 0 0
R R R R
4 3 2 1
— — — —
0 0 0 0
R R R R
16
—
0
R
0
TXQE
0
R/W
21-100