Irq Interrupt Request Register (Irqrr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.3.3

IRQ Interrupt Request Register (IRQRR)

IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set
for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the
retained interrupts.
Bit: 15
-
0
Initial value:
R/W:
R
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit Bit Name
15 to 8 ―
7 IRQ7F
6 IRQ6F
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
[Legend]
n = 7 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
9 8 7 6 5
- - IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0 0 0 0 0
R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Description
Reserved
These bits are always read as 0. The write value should always be 0.
IRQ Interrupt Request
These bits indicate the status of the IRQ7 to IRQ0 interrupt requests.
Level detection:
0: IRQn interrupt request has not occurred
[Clearing condition]
• IRQn input is high
1: IRQn interrupt has occurred
[Setting condition]
• IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing condition]
• Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF
1: IRQn interrupt request is detected
[Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at
IRQn pin
7. Interrupt Controller
4 3 2 1 0
0 0 0 0 0
7-15