Serial Data Transmission (Clock Synchronous Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.5.4

Serial Data Transmission (Clock Synchronous Mode)

Figure 15.19 shows an example of the operation for serial transmission in clock synchronous mode.
In serial data transmission, the SCI operates as described below.
1. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The
TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE
bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
2. After transferring data from TDR to TSR, the SCI starts transmission. When the SCR.TIE bit is set to 1 at this time,
a TXI interrupt request is generated. Continuous transmission is enabled by writing the next transmit data to TDR in
this TXI interrupt processing routine before transmission of the current transmit data has finished. When TEI
interrupt requests are in use, set the SCR.TIE bit to 0 (disabling TXI requests) and the SCR.TEIE bit to 1 (enabling
TEI requests) after the last of the data to be transmitted are written to the TDR from the processing routine for TXI
requests.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when clock output mode has been
specified and in synchronization with the input clock when use of an external clock has been specified. Output of
the clock signal is suspended until the input CTS signal is at the low level while the CTSE bit in SECR is 1
(enabling the CTS function).
4. The SCI checks for updating of (writing to) the TDR at the time of the last bit output.
5. When TDR is updated, the next transmit data is transferred from TDR to TSR, and serial transmission of the next
frame is started.
6. If TDR is not updated, set the SSR flag in TEND to 1 and the TXDn pin retains the output state of the last bit. If the
TEIE bit in SCR is 1 at this time, a TEI interrupt request is generated. The SCKn pin is held high.
Figure 15.20 shows a sample flowchart of serial data transmission.
Transmission will not start while a receive error flag (ORER, FER, or PER in SSR) is set to 1. Be sure to clear the receive
error flags to 0 before starting transmission. Note that clearing the RE bit in SCR to 0 does not clear the receive error
flags.
Synchronization
clock
Serial data
TXI interrupt flag
SSR.TEND flag
TXI interrupt
request
generated
Figure 15.19 Example of Operation for Serial Transmission in Clock Synchronous Mode (from the Middle of
Transmission until Transmission Completion)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit 0 Bit 1 Bit 7
Data written to TDR in
TXI interrupt processing
routine
1 frame
Bit 0 Bit 1 Bit 7
(TIE = 1)
TXI interrupt
Data written to TDR in TXI
request
interrupt processing routine
generated
(Set the TIE bit to 0 and the
TEIE bit to 1 after writing the
last data)
15. Serial Communications Interface
Bit 1 Bit 7
Bit 0
(TIE = 0)
TEI interrupt
request
generated
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