Remap Register (Rmpr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.1

Remap Register (RMPR)

This register controls the address remapping function.
Bit:
31
—
Initial value: 0
R/W:
R
Bit:
15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 to 2 —
1 AXI128
0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
— — — — —
0 0 0 0
R R R R
14 13 12 11 10
— — — — —
0 0 0 0
R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
1 R/W AXI128 Address Remapping
This bit enables or disables allocation of addresses H'0000_0000 to H'009F_FFFF
to on-chip RAM pages 0 to 4 (pages 0 to 3 in the RZ/A1LC).
0: Address remapping is enabled.
1: Address remapping is disabled.
1 R Reserved
This bit is always read as 1. The write value should always be 1.
25 24 23 22
— — — —
0 0 0 0 0
R R R R R
9 8 7 6
— — — —
0 0 0 0 0
R R R R R
5. LSI Internal Bus
21 20 19 18 17
— — — — —
0 0 0 0 0
R R R R R
5 4 3 2 1
— —
— —
AXI128
0 0 0 0 1
R R R R R/W
16
—
0
R
0
—
1
R
5-15