Rscan0Cmerfl - Channel Error Flag Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.4 RSCAN0CmERFL — Channel Error Flag Register (m = 0 or 1)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 000C
Initial value: 0000 0000
Bit 31 30 29
—
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— ADERR B0ERR B1ERR CERR
0 0 0
Initial value
1
R/W R R/W* R/W*
Note 1.
Table 21.18
Bit Position
31
30 to 16
15
14
13
12
11
10
9
8
7
6
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0010 )
H H
H
28 27 26
0 0 0
R R R
12 11 10
AERR FERR
0 0 0
1 1 1 1
R/W* R/W* R/W* R/W*
The only effective value for writing to this flag bit is 0, which clears the bit. Otherwise writing to the bit results
in retention of its state.
RSCAN0CmERFL register contents (1/2)
Bit Name Function
Reserved This bit is always read as 0. The write value should always be 0.
CRCREG[14:0] CRC Calculation Data
A CRC value calculated based on the transmit message or receive message is
indicated.
Reserved This bit is always read as 0. The write value should always be 0.
ADERR ACK Delimiter Error Flag
0: No ACK delimiter error is detected.
1: ACK delimiter error is detected.
B0ERR Dominant Bit Error Flag
0: No dominant bit error is detected.
1: Dominant bit error is detected.
B1ERR Recessive Bit Error Flag
0: No recessive bit error is detected.
1: Recessive bit error is detected.
CERR CRC Error Flag
0: No CRC error is detected.
1: CRC error is detected.
AERR ACK Error Flag
0: No ACK error is detected.
1: ACK error is detected.
FERR Form Error Flag
0: No form error is detected.
1: Form error is detected.
SERR Stuff Error Flag
0: No stuff error is detected.
1: Stuff error is detected.
ALF Arbitration-lost Flag
0: No arbitration-lost is detected.
1: Arbitration-lost is detected.
BLF Dominant Lock Flag
0: No dominant lock is detected.
1: Dominant lock is detected.
25 24 23 22
CRCREG[14:0]
0 0 0 0
R R R R
9 8 7 6
SERR ALF BLF
0 0 0 0
1 1 1 1
R/W* R/W* R/W*
21. CAN Interface
21 20 19 18
0 0 0 0
R R R R
5 4 3 2
OVLF BORF BOEF EPF
0 0 0 0
1 1 1 1
R/W* R/W* R/W* R/W*
17 16
0 0
R R
1 0
EWF BEF
0 0
1 1
R/W* R/W*
21-28