Fc Status Register (Ssifcsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.12

FC Status Register (SSIFCSR)

SSIFCSR consists of the frequency change detection status flag and the bits that indicate the current cycle count of the
peripheral clock 1 (P1φ).
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value: 0
R/W:
R
Bit Bit Name
31 to 25 ―
24 FCIRQ
23 to 14 ―
13 to 0 VALUE
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
-
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/(W)*
All 0 R
0 R
25 24 23 22 21
- FCIRQ - -
0 0 0 0
R R/(W)* R R R
9 8 7 6
VALUE
0 0 0 0
R R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Frequency Change Detection Error Interrupt Status
Indicates VALUE > SSIFCMR.MAXV or 0 < VALUE < SSIFCMR.MINV when
SSIFCCR.FCEN = 1.
This bit is set to 1 regardless of the setting of the FIEN bit in SSIFCCR. Write
0 to clear this flag to 0.
When FCIRQ = 1 and SSIFCCR.FIEN = 1, an SSI interrupt is generated.
Reserved
These bits are always read as 0. The write value should always be 0.
VALUE
Indicates the current cycle count of the peripheral clock 1 (P1φ) in an SSIWS
cycle, when SSIFCCR.FCEN = 1. Each time the next SSIWS cycle starts,
the value is updated.
Note: When the SSISCK signal stops, the start of an SSIWS cycle cannot be
detected. Consequently, the value is not updated.
19. Serial Sound Interface
20 19 18 17
- - - - -
0 0 0 0 0
R R R R
5 4 3 2 1
0 0 0 0 0
R R R R
16
-
0
R
0
0
R
19-21